Hello, I'm

Zeb Taylor

I'm a computer engineering student at the University of Wisconsin-Madison.

01 Work & Education

This summer (2026) I worked as an intern at Draper's digital ASIC team in Cambridge, MA. I have experience with design, synthesis, and implementation of digital designs, predominantly using SystemVerilog. I am looking to specialize in computer architecture, but am open to other areas in digital design.

I'm currently an incoming freshman at the University of Wisconsin-Madison, but prior to that I took classes at the University of Minnesota-Twin Cities, including Advanced Computer Architecture, Modern Algebra, and Environmental Philosophy (among many others).

02 Projects

DLGN-Enhanced Branch Prediction

PyTorch · CUDA · 2025

A variation of Differentiable Logic Gate Networks that learns gate wirings, applied to the BranchNet predictor for a graduate Advanced Computer Architecture capstone. Matched or exceeded BranchNet on CBP2025 hard-to-predict branches.

RISC-V CPU

SystemVerilog · Basys 3 · 2026

A five-stage pipelined RV32I CPU that runs a boids simulation written in C. Includes an internal pipeline signal display over VGA for real-time monitoring, and uses Object Attribute Memory to ease memory constraints on the Basys 3.

Boids simulation running on the RISC-V CPU, with VGA pipeline signal display

Custom ISA Out of Order Processor

SystemVerilog · Basys 3 · 2025

A custom 8-bit ISA, single-issue out of order processor written in SystemVerilog. Uses an 8-stage pipeline including fetch, decode, rename, issue, reservation, execution, reorder, and commit.

View repo

Systolic Array GeMM Accelerator

Chisel · OpenLane · SkyWater 130nm · 2026

A parameterizable systolic-array matrix-multiply accelerator targeting 32×32 matrices. Compared a baseline design against a Strassen-based implementation across fixed-point and floating-point datatypes, evaluating power, performance, and area with OpenLane on the SkyWater 130nm PDK.

Bad Apple!! Chip Art

OpenROAD · Yosys · SkyWater 130nm · 2026

A synthesizable RISC-V core placed and routed into a Sky130 floorplan shaped like each frame of Bad Apple!!. Black pixels become hard placement blockages; white pixels are the only legal cell area. OpenROAD then implements Ibex, PicoRV32, or SERV into that silhouette, and the routed stills are compiled into a movie.

RISC-V cores placed and routed into Bad Apple!! silhouettes on Sky130

03 About

Portrait of Zeb Taylor

I'm ENTJ-A, and very passionate about the things I enjoy. I can talk for hours about computer engineering, philosophy, science in general, politics, and economics. I am a utlitarian, market-oriented leftist, and believer that P=NP. My favorite TV shows include Last Week Tonight, The Good Place, and Parks and Recreation.

My go-to fun facts include: you can become drunk under high pressure nitrogen, a 5 month old bird flew nonstop from Alaska to Tasmania in 11 days, and the earth's magnetic field is 60% weaker over South America.

04 Hobbies

Chocolate babka baked by Zeb Taylor

I enjoy baking, cooking, hiking, and playing video games. On the right is a picture of some babka I made. Baking breads is always a challenge, but when they turn out well they are delicious.

A heron seen while canoeing on the Mississippi

I have also gotten into birdwatching recently. On the left is a picture of a heron a friend and I saw while canoing on the Mississippi. (Click the picture to enlarge it.)

05 Contact

Email is the best way to get in touch.

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